1 ps8542 06/20/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c2952 description the pi6c2952 is a 3.3v compatible, pll-based clock driver device targeted for high-performance clock applications. the device fea- tures a fully integrated pll with no external components required. with output frequencies up to 180mhz and eleven low- skew outputs, the pi6c2952 is well suited for high-performance designs. the device employs a fully differential pll design to optimize jitter and noise rejection performance. the pi6c2952 features three banks of individually configurable outputs. the banks contain 5 outputs, 4 outputs, and 2 outputs. the internal divide circuitry allows for output frequency ratios of 1:1, 2:1, 3:1, and 3:2:1. the output frequency relationship is controlled by the fsel frequency control pins. the fsel pins and other inputs are lvcmos/lvttl compatible inputs. the pi6c2952 uses external feedback to the pll. this features allows the device to be used as a ?zero delay? buffer. any of the eleven outputs can be used as feedback to the pll. to optimize pll stability and jitter performance,the vco_sel pin allows for the choice of two vco ranges. for board level test, the mr/oe pin allows a user to force the outputs into high impedance. for system debug, the pi6c2952?s pll can be bypassed. when forced to a logic high, the pllen input routes the signal on the refclk input around the pll directly to the internal dividers. because the signal is routed through the dividers, it may take several transitions of the refclk to affect a transition on the outputs. this features allows a designer to single step the design for debug purposes. the pi6c2952?s outputs are lvcmos which are optimally designed to drive terminated transmission lines. for applications using series- terminated transmission lines, each pi6c2952 output can drive two lines. this capability provides an effective fanout of 22, more than enough clocks for most clock tree designs. features ? 100ps cycle-to-cycle jitter ? fully integrated pll ? output frequency up to 180mhz ? high-impedance disabled outputs ? compatible with powerpc, intel and high performance risc microprocessors ? configurable output frequency ? 32-pin lqfp package (fb) pin configuration low voltage pll clock driver 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 25 26 27 28 29 30 31 32 vcco qb2 qb3 gndo gndo qc0 qc1 vcco gndo qb1 qb0 vcco vcco qa4 qa3 gndo vco_sel fselc fselb fsela mr/oe refclk gndi fbin vcco qa2 qa1 gndo qa0 vcci vcca pll_en 32-pin fb
2 ps8542 06/20/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c2952 low voltage pll clock driver fsela (int pull down) (int pull down) (int pull down) fselb (int pull down) fselc (int pull down) mr/oe (int pull down) vco_sel pll_en fbin refclk vco 200-480mhz v v v qa4 qa3 qa2 qa1 qa0 qb3 qb2 qb1 qb0 qc1 qc0 2 "C1" has 2/8 "C2" has 4/8 4/2 4/6 phase detector lpf 2/4 function tables a l e s fn a qb l e s fn b qc l e s fn c q 0 1 4 6 0 1 4 2 0 1 2 4 n i p l o r t n o c' o ' c i g o l' 1 ' c i g o l l e s _ o c vo c v f2 / o c v f e o / r me l b a n e t u p t u oz h g i h n e _ l l pl l p e l b a n el l p e l b a s i d e m a n n i pn o i t p i r c s e d a c c vy l p p u s r e w o p l l p o c c vy l p p u s r e w o p r e f f u b t u p t u o i c c vy l p p u s r e w o p c i g o l e r o c l a n r e t n i i d n gd n u o r g l a n r e t n i o d n gd n u o r g r e f f u b t u p t u o block diagram
3 ps8542 06/20/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c2952 low voltage pll clock driver absolute maximum ratings* l o b m y ss r e t e m a r a p. n i m. x a ms t i n u v c c e g a t l o v y l p p u s3 . 0 ?6 . 4 v v i e g a t l o v t u p n i3 . 0 ?v d d 3 . 0 + i n i t n e r r u c t u p n i 0 2 a m t r o t s e g n a r e r u t a r e p m e t e g a r o t s0 4 ?5 2 1c pll input reference characteristics (t a = 0c to 70c) l o b m y ss r e t e m a r a p. n i m. x a ms t i n un o i t i d n o c t r t , f s l l a f / e s i r t u p n i k l c t0 . 3s n f f e r y c n e u q e r f t u p n i e c n e r e f e r. 3 e t o n. 3 e t o nz h m f c d f e r e l c y c y t u d t u p n i e c n e r e f e r5 25 7% *absolute maximum continuous ratings are those values beyond which damage to the device may occur. exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. functional operation under absolute-maximum-rated conditions is not implied. 3. maximum and minimum input reference is limited by the v co lock range and the feedback divider. dc characteristics (t a = 0c to 70 c, v cc = 3.3v 5%) l o b m y ss n o i t i d n o cc i t s i r e t c a r a h c. n i mp y t. x a ms t i n u v h i e g a t l o v h g i h t u p n i0 . 26 . 3 v v l i e g a t l o v w o l t u p n i8 . 0 v h o i h o ) . 1 e t o n ( a m 0 2 =e g a t l o v h g i h t u p t u o4 . 2 v l o i l o ) . 1 e t o n ( a m 0 2 =e g a t l o v w o l t u p t u o5 . 0 i n i . 2 e t o nt n e r r u c t u p n i0 2 1 a m c n i e c n a t i c a p a c t u p n i7 . 20 . 4 f p c d p e c n a t i c a p a c n o i t a p i s s i d r e w o p5 2 i c c t n e r r u c c i t a t s c c i l a t o tt n e r r u c y l p p u s t n e c s e i u q m u m i x a m0 6 1 a m i a c c t n e r r u c y l p p u s l l p5 10 2 notes: 1. the pi6c2952 outputs can drive series- or parallel-terminated 50 ohms (or 50 ohms to v cc /2) transmission lines on the incident edge (see applications info section). 2. inputs have pull?up, pull?down resistors that affect input current.
4 ps8542 06/20/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c2952 low voltage pll clock driver l o b m y ss c i t s i r e t c a r a h cs n o i t i d n o c. n i m. p y t. x a ms t i n u f t , r t) . 4 e t o n ( e m i t l l a f / e s i r t u p t u ov 0 . 2 o t 8 . 00 1 . 00 . 1s n i w p ) . 4 e t o n ( h t d i w e s l u p t u p t u o t e l c y c 2 / 0 5 7 ? t e l c y c 2 / 0 0 5 t e l c y c 2 / 0 5 7 + s p t s o ) . 4 e t o n ( 0 a q g n i d u l c x e w e k s t u p t u o - o t - t u p t u o s t u p t u o l l a s t u p t u o l l a s e i c n e u q e r f e m a s s e i c n e u q e r f e m a s s e i c n e u q e r f t n e r e f f i d 0 5 3 0 5 4 0 5 5 f o c v 4 / o c v = k c a b d e e f e g n a r k c o l o c v l l p 6 / o c v = k c a b d e e f 8 / o c v = k c a b d e e f 2 1 / o c v = k c a b d e e f 0 = l e s _ o c v 0 = l e s _ o c v 1 = l e s _ o c v 1 = l e s _ o c v 0 0 2 0 0 2 0 0 2 0 0 2 0 8 4 0 8 4 0 8 4 0 8 4 z h m f x a m y c n e u q e r f t u p t u o m u m i x a m ) 2 ( b q , c q ) 4 ( c q , b q , a q ) 6 ( a q ) . 4 e t o n ( 0 8 1 0 2 1 0 8 z h m d p ty a l e d n i b f o t k l c f e r. 5 , . 4 s e t o n0 0 2 ?00 0 2s p t z l p t , z h p e m i t e l b a s i d t u p t u ov o t s m h o 0 5 c c 2 /2 8 s n t l z p t , h z p e m i t e l b a n e t u p t u ov o t s m h o 0 5 c c 2 /2 0 1 r e t t i j t) k a e p ? o t ? k a e p ( r e t t i j e l c y c ? o t ? e l c y c 0 0 1 s p t k c o l e m i t k c o l l l p m u m i x a m. 5 e t o n0 1s m t p j r e t t i j d o i r e p m r e t g n o l d b ts p ac characteristics (t a = 0c to 70c, v cc = 3.3v 5%) 4. 50ohms to v cc /2. 5. t pd is specified for 50mhz input ref, the window will shrink/grow proportionally from the minimum limit with shorter/longer input reference periods. the t pd does not include jitter. applications information driving transmission lines the pi6c2952 clock driver was designed to drive high-speed signals in a terminated transmission line environment. to provide the optimum flexibility to the user, the output drivers were designed to exhibit the lowest impedance possible. with an output impedance of less than 10 ohms, the drivers can drive either parallel- or series-terminated transmission lines. figure 3. single versus dual transmission lines pi6c2952 output buffer pi6c2952 output buffer 7 ohms 7 ohms in in outa outb0 outb1 r s = 43 ohms r s = 43 ohms r s = 43 ohms z o = 50 ohms z o = 50 ohms z o = 50 ohms
5 ps8542 06/20/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c2952 low voltage pll clock driver in most high performance clock networks point?to?point distribu- tion of signals is the method of choice. in a point?to?point scheme either series terminated or parallel terminated transmission lines can be used. the parallel technique terminates the signal at the end of the line with a 50ohm resistance to v cc /2. this technique draws a fairly high level of dc current and thus only a single terminated line can be driven by each output of the pi6c2952 clock driver. for the series terminated case however there is no dc current draw, thus the outputs can drive multiple series terminated lines. figure 3 illustrates an output driving a single series terminated line vs two series terminated lines in parallel. when taken to its extreme the fanout of the pi6c2952 clock driver is effectively doubled due to its capability to drive multiple lines. the waveform plots of figure 4 show the simulation results of an output driving a single line vs two lines. in both cases the drive capability of the pi6c2952 output buffers is more than sufficient to drive 50ohm transmission lines on the incident edge. note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. this suggests that the dual line driving need not be used exclusively to maintain the tight output?to?output skew of the pi6c2952. the output waveform in figure 4 shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. the parallel combination of the 43ohm series resistor plus the output impedance does not match the parallel combination of the line impedances. the voltage wave launched down the two lines will equal: vl = vs (zo / rs + ro +zo) = 3.0 (25/53.5) = 1.40v at the load end the voltage will double, due to the near unity reflection coefficient, to 2.8v. it will then increment towards the quiescent 3.0v in steps separated by one round trip delay (in this case 4.0ns). 0.5 1.0 1.5 2.0 2.5 3.0 0 24 6 8 10 12 14 time (ns) outa t d = 3.8956 outb t d = 3.9386 t rip delay (in this case 4.0ns). voltage (v) in figure 4. single versus dual waveforms since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. to better match the impedances when driving multiple lines the situation in figure 5 should be used. in this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer imped- ance the line impedance is perfectly matched. pi6c2952 output buffer 7ohm r s =36ohm r s =36ohm z o =50ohm z o =50ohm 7ohm + 36ohm ? 36ohm = 50ohm ? 50ohm 25ohm = 25ohm ? figure 5. optimized dual line termination spice level output buffer models are available for engineers who want to simulate their specific interconnect schemes. in addition iv characteristics are in the process of being generated to support the other board level simulators in general use. power supply filtering the pi6c2952 is a mixed analog/digital product and as such it exhibits some sensitivities that would not necessarily be seen on a fully digital product. analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. the pi6c2952 provides separate power supplies for the output buffers (v cco ) and the internal pll (v cca ) of the device. the purpose of this design technique is to try and isolate the high switching noise digital outputs from the relatively sensitive internal analog phase?locked loop. in a controlled environment such as an evaluation board this level of isolation is sufficient. however, in a digital system environ- ment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. the simplest form of isolation is a power supply filter on the v cca pin for the pi6c2952.
6 ps8542 06/20/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c2952 low voltage pll clock driver 3.3v r s = 5-15 ohms 22f 0.01f 0.01f vcca vcc pi6c2952 figure 6. power supply filter seating plane 0.80 bsc .032 0.30 0.45 .012 .018 1.60 .063 1.35 1.45 .053 .057 x.xx x.xx denotes dimensions in millimeters 9.00 bsc .276 square 7.00 bsc .354 square gauge plane 1.00 ref .039 0.45 0.75 .018 .030 0.09 0.20 .004 .008 0 7 0.25 mm max. 0.10 .004 0.05 0.15 .002 .006 package drawing r e b m u n t r a pe g a k c a pe r u t a r e p m e t g n i t a r e p o b f 2 5 9 2 c 6 i p p f q l - 2 3l a i c r e m m o c b f 1 - 2 5 9 2 c 6 i p b f 2 - 2 5 9 2 c 6 i p ordering information pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com
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